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【DK-SI-5SGXEA7N/S5GSI】Altera Transceiver Signal Integrity開(kāi)發(fā)板
- 產(chǎn)品型號(hào)： DK-SI-5SGXEA7N/S5GSI（Part No:T0118）
- 產(chǎn)品品牌： TERASIC友晶科技/Intel FPGA
- 產(chǎn)品規(guī)格： Stratix V GX FPGA:5SGXEA7N2F40C2N
- 產(chǎn)品價(jià)格： 歡迎咨詢(xún)采購(gòu)，量多優(yōu)惠多，提供完善的售后保障和支持！
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The Altera® Stratix® V GX Transceiver Signal Integrity (SI) Development Kit provides a platform for electrical compliance testing and interoperability analysis. The accessibility to multiple channels allows for real-world analysis as implemented in the system with transceiver channels available through SMA and popular backplane connectors. You can use this development kit to perform the following tasks:
Evaluate transceiver link performance from 600 Mbps to 12.5 Gbps
Generate and check pseudo-random binary sequence (PRBS) patterns via a simple to use GUI (does not require the Quartus® II software)
Access advanced equalization to fine tune link settings for optimal bit error ratio (BER)
Perform jitter analysis
Verify physical medium attachment (PMA) compliance to 10GbE, 10GBASE-KR, PCI Express® (PCIe®)(Gen1, Gen2, and Gen3), Serial RapidIO®, Gigabit Ethernet, 10-Gigabit Ethernet XAUI, Common Electrical I/O (CEI) 6G, CEI-11G, high-definition serial digital interface (HD-SDI), Interlaken, and other major standards
Use the built-in high speed backplane connectors to evaluate custom backplane performance and evaluate link BER
Featured device
Configuration status and set-up elements
Clocks
General user input/output
Memory devices
High speed serial interfaces
Power
Stratix V GX Transceiver Signal Integrity Development Board Block Diagram
Laptop DC input
Voltage margining
Seven channels to Molex® Impact® connector
Seven channels to Amphenol® XCede®
Seven channels to footprint of Tyco Strada® Whisper® (connector is not populated)
Short trace routed on a micro-strip
Six strip-line channels from the with all the trace lengths are matched across channels
Seven full-duplex transceiver channels routed to SMA connectors
21 full-duplex transceiver channels routed to backplane connector
128-megabyte (MB) sync flash memory (primarily to store FPGA configurations)
10-/100-/1000-Mbps Ethernet PHY (RGMII) with RJ-45 (copper) connector
16x2 character LCD
One 8-postion dipswitch
Eight user LEDs
Four user pushbuttons
50 MHz, 125 MHz, programmable oscillators (preset values: 624 MHz, 644.5 MHz, 706.25 MHz, and 875 MHz)
SMA connectors for supplying an external differential clock to transceiver reference clock
SMA connectors for supplying an external differential clock to the FPGA fabric
SMA connectors to output a differential clock from the FPGA's phase-locked loop (PLL) output pin
JTAG
On-board USB-BlasterTM
Fast passive parallel (FPP) configuration via MAX® II device and flash memory
Two configuration file storage
Temperature measurement circuitry (die and ambient temperature)
5SGXEA7N2F40C2N
| No | 產(chǎn)品名稱(chēng) | 售價(jià)(RMB) |
|---|---|---|
| 1. |
[S5GSI] Altera Transceiver Signal Integrity Development Kit, Stratix V GT Edition
產(chǎn)品編號(hào): T0118  重量: 4,000g | xxx |
Documents
| 標(biāo)題 | 版本 | 檔案大小(KB) | 新增日期 | 下載 |
|---|---|---|---|---|
| Signal Integrity Development Kit, Stratix V GX Edition User Guide (PDF) | 11.0.2 | 2013-01-03 |  | |
| Transceiver Signal Integrity Development Kit, Stratix V GX Edition Reference Manual | 11.0.2 | 2013-01-03 | |
CD-ROM
| 標(biāo)題 | 版本 | 檔案大小(KB) | 新增日期 | 下載 |
|---|---|---|---|---|
| Kit installation (for boards with ES silicon) | 11.1.2 | 2013-01-03 |  | |
| Kit installation | 12.0 | 2013-01-03 | |