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[C5EFP+DVI] Cyclone V E Video Development System
- 產(chǎn)品型號(hào)： C5EFP+DVI（Part No:K0117）
- 產(chǎn)品品牌： TERASIC友晶科技/Intel FPGA
- 產(chǎn)品規(guī)格： Cyclone V E FPGA - 5CEFA7F31C7NES
- 產(chǎn)品價(jià)格： 歡迎咨詢采購(gòu)，量多優(yōu)惠多，提供完善的售后保障和支持！
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The Cyclone V E Video Development System is an ideal video processing platform for high-performance, cost-effective video applications. The Cyclone® V E Development Kit offers a comprehensive general purpose development platform for many markets and applications. With multiple banks of DDR3 and LPDDR2 memory, this kit provides the ideal low-cost platform for high-bandwidth video processing. Additional features include an LCD character display, LEDs, user switches, USB and RJ-45 connectors.
The DVI-HSMC daughter card part of the bundled package will allow developers to access high quality and high resolution video signals that can support resolution up to 1600x1200. A complete DVI video controller design with source code is provided.
Terasic recognized for its strong design expertise in high-end video, imaging and multimedia products have made available a video development package that targets video processing development. The platform can also allow users to experience advanced image processing designs incorporating VIP (Altera’s Video and Image Processing Suite MegaCore Functions).
Altera Cyclone V E Video Development System
Featured devices:
Cyclone V E FPGA - 5CEFA7F31C7NES
MAX V CPLD - 5M2210ZF256I5N (system controller)
MAX II CPLD - EPM240M100I5N (embedded USB Blaster II)
Configuration:
On-board USB-BlasterTM II cable (USB, PHY, Max® V CPLD)
JTAG direct via JTAG header
Memory devices
DDR3 x32 at 300 MHz (soft memory controller)
LPDDR2 x16 (soft memory controller)
Flash (512 Mb)
SSRAM (18 Mb)
EEPROM (64 Kb)
General user input/output
User control
Four pushbuttons
Five LEDs
Four DIP switches
2x Resets (CPU reset, Dev Clear)
LCD: Character LCD (16x2)
Components and interfaces
RJ45 for Ethernet
UART interface
Quartus® II design software information
Quartus II Web Edition Software
Altera Cyclone V E FPGA Development Board Block Diagram
Terasic DVI-HSMC Card
Digital Transmitter
One DVI transmitter with single transmitting port
Digital Visual Interface (DVI) Compliant
Supports resolutions from VGA to UXGA (25 MHz – 165 MHz Pixel Rates)
Universal Graphics Controller Interface
12-Bit, Dual-Edge and 24-Bit, Single-Edge Input Modes
Adjustable 1.1 V to 1.8 V and Standard 3.3 V CMOS Input Signal Levels
Fully Differential and Single-Ended Input Clocking Modes
Standard Intel 12-Bit Digital Video Port Compatible as on Intel™ 81x Chipsets
Enhanced PLL Noise Immunity
On-Chip Regulators and Bypass Capacitors for Reducing System Costs
Enhanced Jitter Performance
Programmable Using I²C Serial Interface
Single 3.3-V Supply Operation
No HSYNC Jitter Anomaly
Negligible Data-Dependent Jitter
Digital Receiver
One DVI receiver with single receiving port
Supports UXGA Resolution (Output Pixel Rates Up to 165 MHz)
Digital Visual Interface (DVI) Specification Compliant
True-Color, 24 Bit/Pixel, 16.7M Colors at 1 or 2-Pixels Per Clock
Laser Trimmed Internal termination Resistors for Optimum Fixed Impedance Matching
4x Over-Sampling
Reduced Ground Bounce Using Time Staggered Pixel Outputs
Lowest Noise and Best Power Dissipation Using TI PowerPAD™ Packaging
| No | 產(chǎn)品名稱 | 售價(jià)(RMB) |
|---|---|---|
| 1. |
[C5EFP+DVI] Cyclone V E Video Development System
產(chǎn)品編號(hào): K0134  重量: 4,000g | xxx |
Documents
| 標(biāo)題 | 版本 | 檔案大小(KB) | 新增日期 | 下載 |
|---|---|---|---|---|
| Cyclone V E FPGA Development Kit User Guide (PDF) | 2013-01-08 |  | ||
| Cyclone V E FPGA Development Board Reference Manual (PDF) | 2013-01-08 | |
CD-ROM
| 標(biāo)題 | 版本 | 檔案大小(KB) | 新增日期 | 下載 |
|---|---|---|---|---|
| DVI Combo CD-ROM | 2013-02-01 | |||
| Kit installation | 2013-01-08 |  |